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application note ds037 (v1.3) october 9, 2000 www.xilinx.com 1 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. features ? industry's first totalcmos? pld - both cmos design and process technologies fast zero power (fzp?) design technique provides ultra-low power and very high speed 3v, in-system programmable (isp) using a jtag interface - on-chip supervoltage generation - isp commands include: enable, erase, program, verify - supported by multiple isp programming platforms - four pin jtag interface (tck, tms, tdi, tdo) - jtag commands include: bypass, idcode high- speed pin-to-pin delays of 7.5 ns ultra-low static power of less than 100 a 5v tolerant i/os to support mixed voltage systems 100% routable with 100% utilization while all pins and all macrocells are fixed deterministic timing model that is extremely simple to use up to 12 clocks available programmable clock polarity at every macrocell support for complex asynchronous clocking innovative xpla? architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed logic expandable to 37 product terms advanced 0.35 e 2 cmos process security bit prevents unauthorized access design entry and verification using industry standard and xilinx cae tools reprogrammable using industry standard device programmers innovative control term structure provides either sum terms or product terms in each logic block for: - programmable 3-state buffer - asynchronous macrocell register preset/reset - up to two asynchronous clocks programmable global 3-state pin facilitates "bed of nails" testing without using logic resources available in plcc, vqfp, and chip scale bga packages industrial grade operates from 2.7v to 3.6v description the xcr3064a cpld (complex programmable logic device) is the second in a family of coolrunner ? cplds from xilinx. these devices combine high speed and zero power in a 64 macrocell cpld. with the fzp design tech- nique, the xcr3064a offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 a at standby without the need for "turbo bits" or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any compet- ing cpld. these devices are the first totalcmos plds, as they use both a cmos process technology and the pat- ented full cmos fzp design technique. the xilinx fzp cplds utilize the patented xpla (extended programmable logic array) architecture. the xpla architecture combines the best features of both pla and pal type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla structure in each logic block provides a fast 7.5 ns pal path with five dedicated product terms per output. this pal path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated effi- ciently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 1.5 ns, regardless of the number of pla product terms used, which results in worst case t pd ? s of only 9.0 ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the xcr3064a cplds are supported by industry standard cae tools (cadence/orcad, exemplar logic, mentor, synopsys, synario, viewlogic, and synplicity), using text (abel, vhdl, verilog) and/or schematic entry. design ver- ification uses industry standard simulators for functional and timing simulation. development is supported on per- sonal computer, sparc, and hp platforms. device fitting uses a xilinx developed tool, xpla professional (available on the xilinx web site). 0 xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 0 14* product specification r
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 2 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. the xcr3064a cpld is reprogrammable using industry standard device programmers from vendors such as data i/o, bpmicrosystems, sms, and others. the xcr3064a also includes an industry-standard, ieee 1149.1, jtag interface through which in-system programming (isp) and reprogramming of the device are supported. xpla architecture figure 1 shows a high level block diagram of a 64 macro- cell device implementing the xpla architecture. the xpla architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a vir- tual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macro- cells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner ? family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the six control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. in addition, two of the control terms can be used as clock signals (see macrocell archi- tecture section for details). the pal array consists of a pro- grammable and array with a fixed or array, while the pla array consists of a programmable and array with a pro- grammable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has five dedicated product terms from the pal array. the pin-to-pin t pd of the xcr3064a device through the pal array is 7.5 ns. if a macrocell needs more than five product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macro- cells. the additional propagation delay incurred by a mac- rocell using one or all 32 pla product terms is just 1.5 ns. so the total pin-to-pin t pd for the xcr3064a using six to 37 product terms is 9.0 ns (7.5 ns for the pal + 1.5 ns for the pla). figure 1: xilinx xpla cpld architecture logic block i/o 36 16 16 36 16 16 mc1 mc2 mc16 i/o mc1 mc2 mc16 sp00439 zia logic block logic block i/o 36 16 16 mc1 mc2 mc16 36 16 16 i/o mc1 mc2 mc16 logic block
r xcr3064a: 64 macrocell cpld with enhanced clocking 3 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. figure 2: xilinx xpla logic block architecture to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 4 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner xcr3064a. the macrocell can be config- ured as either a d- or t-type flip-flop or a combinatorial logic function. a d-type flip-flop is generally more useful for implementing state machines and data buffering while a t-type flip-flop is generally more useful in implementing counters. each of these flip-flops can be clocked from any one of six sources. four of the clock sources (clk0, clk1, clk2, clk3) are connected to low-skew, device-wide clock networks designed to preserve the integrity of the clock signal by reducing skew between rising and falling edges. clock 0 (clk0) is designated as a "synchronous" clock and must be driven by an external source. clock 1 (clk1), clock 2 (clk2), and clock 3 (clk3) can be used as "synchronous" clocks that are driven by an external source, or as "asynchronous" clocks that are driven by a macrocell equation. clk0, clk1, clk2, and clk3 can clock the macrocell flip-flops on either the rising edge or the falling edge of the clock signal. the other clock sources are two of the six control terms (ct2 and ct3) provided in each logic block. these clocks can be individually configured as either a product term or sum term equation created from the 36 signals available inside the logic block. the tim- ing for asynchronous and control term clocks is different in that the t co time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t su time is reduced. p the six control terms of each logic block are used to control the asynchronous preset/reset of the flip-flops and the enable/disable of the output buffers in each macrocell. control terms ct0 and ct1 are used to control the asyn- chronous preset/reset of the macrocell ? s flip-flop. note that the power-on reset leaves all macrocells in the "zero" state when power is properly applied, and that the pre- set/reset feature for each macrocell can also be disabled. control terms ct2 and ct3 can be used as a clock signal to the flip-flops of the macrocells, and as the output enable of the macrocell ? s output buffer. control terms ct4 and ct5 can be used to control the output enable of the mac- rocell ? s output buffer. having four dedicated output enable control terms ensures that the coolrunner devices are pci compliant. the output buffers can also be always enabled or always disabled. all coolrunner devices also provide a global 3-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support "in-circuit testing" or "bed-of-nails testing". there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin feedback path. when the macrocell is used as an out- put, the output buffer is enabled, and the macrocell feed- back path can be used to feedback the logic implemented in the macrocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic imple- mented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated (see the section on ? terminations ? on page 8 in this data sheet and the application note terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds ). figure 3: xcr3064a macrocell architecture init (p or r) d/t q sp00558 clk0 clk0 clk1 clk1 to zia gnd ct0 ct1 gts ct2 ct3 ct4 ct5 v gnd cc gnd pal pla clk2 clk2 clk3 clk3
r xcr3064a: 64 macrocell cpld with enhanced clocking 5 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. simple timing model figure 4 shows the coolrunner timing model. the cool- runner timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd ,t su , and t co . in other architectures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependen- cies on the number of parallel expanders borrowed, shar- able expanders, varying number of x and y routing channels used, etc. in the xpla architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. for example, in the xcr3064a device, the user knows up front that if a given output uses 5product terms or less, the t pd = 7.5 ns, the t su_pal = 3.5 ns, and the t co = 5.5 ns. if an output is using six to 37 product terms, an additional 1.5 ns must be added to the t pd and t su tim- ing parameters to account for the time to propagate through the pla array. totalcmos design technique for fast zero power xilinx is the first to offer a totalcmos cpld, both in pro- cess technology and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds which are both high performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. refer to figure 5 and table 1 showing the i cc vs. frequency of our xcr3064a totalcmos cpld. (data taken with four up/down loadable 16-bit counters at 3.3v, 25 c) figure 4: coolrunner timing model output pin input pin sp00441 t pd_pal = combinatorial pal only t t t t pd_pla = combinatorial pal + pla output pin input pin dq registered su_pal = pal only su_pla = pal + pla registered co global clock pin
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 6 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. jtag testing capability jtag is the commonly-used acronym for the boundary scan test (bst) feature defined for integrated circuits by ieee standard 1149.1. this standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of spe- cialized test equipment. the xilinx xcr3064a devices use the jtag interface for in-system programming/repro- gramming. although only a subset of the full jtag com- mand set is implemented (see table 2 ), the devices are fully capable of sitting in a jtag scan chain. the xilinx xcr3064a ? s jtag interface includes a tap port defined by the ieee 1149.1 jtag specification. as imple- mented in the xilinx xcr3064a, the tap port includes four of the five pins (refer to table 4 ) described in the jtag specification: tck, tms, tdi, and tdo. the fifth signal defined by the jtag specification is trst* (test reset). trst* is considered an optional signal, since it is not actu- ally required to perform bst or isp. the xilinx xcr3064a saves an i/o pin for general purpose use by not implement- ing the optional trst* signal in the jtag interface. instead, the xilinx xcr3064a supports the test reset func- tionality through the use of its power up reset circuit, which is included in all xilinx cplds. the pins associated with the tap port should connect to an external pull-up resistor to keep the jtag signs from floating when they are not being used. in the xilinx xcr3064a, the four mandatory jtag pins each require a unique, dedicated pin on the device. the devices come from the factory with these i/o pins set to perform jtag functions, but through the software, the final function of these pins can be controlled. if the end applica- tion will require the device to be reprogrammed at some future time with isp, then the pins can be left as dedicated jtag functions, which means they are not available for use as general purpose i/o pins. however, unlike some other cplds, the xilinx xcr3064a allow the macrocells associ- ated with these pins to be used as buried logic when the jtag/isp function is enabled. this is the default state for the software, and no action is required to leave these pins enabled for the jtag/isp functions. if, however, jtag/isp is not required in the end application, the software can specify that this function be turned off and that these pins be used as general purpose i/o. because the devices ini- tially have the jtag/isp functions enabled, the jedec file can be downloaded into the device once, after which the jtag/isp pins will become general purpose i/o. this fea- ture is good for manufacturing because the devices can be programmed during test and assembly of the end product and yet still use all of the i/o pins after the programming is figure 5: i cc vs. frequency at v cc = 3.3v, 25 c typical i cc (ma) frequency (mhz) sp00700 1 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 45 table 1: i cc vs. frequency (v cc = 3.3v, 25 c) frequency (mhz) 0 1 20 40 60 80 100 120 140 typical i cc (ma) 0.03 0.3 4.7 9.4 14.0 18.7 23.2 27.7 32.4
r xcr3064a: 64 macrocell cpld with enhanced clocking 7 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. done. it eliminates the need for a costly, separate program- ming step in the manufacturing process. of course, if the jtag/isp function is never required, this feature can be turned off in the software and the device can be pro- grammed with an industry-standard programmer, leaving the pins available for i/o functions. ta b l e 3 defines the ded- icated pins used by the four mandatory jtag signals for each of the xcr3064a package types. table 2: xcr3064a low-level jtag boundary-scan commands instruction (instruction code) register used description bypass (1111) bypass register places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation. the bypass instruction can be entered by holding tdi at a constant high value and completing an instruction-scan cycle. idcode (0001) boundary-scan register selects the idcode register and places it between tdi and tdo, allowing the idcode to be serially shifted out of tdo. the idcode instruction permits blind inter- rogation of the components assembled onto a printed circuit board. thus, in circum- stances where the component population may vary, it is possible to determine what components exist in a product. table 3: jtag pin description pin name description tck test clock output clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tms test mode select serial input pin selects the jtag instruction mode. tms should be driven high during user mode operation. tdi test data input serial input pin for instructions and test data. data is shifted in on the rising edge of tck. tdo test data output serial output pin for instructions and test data. data is shifted out on the falling edge of tck. the signal is tri-stated if data is not being shifted out of the device. table 4: xcr3064a jtag pinout by package type device xcr3064a (pin number/macrocell #) tck tms tdi tdo 44-pin plcc 32/c15 13/b15 7/a8 38/d8 44-pin vqfp 26/c15 7/b15 1/a8 32/d8 56-ball csp f10/c15 g1/b15 c1/a8 c10/d8 100-pin vqfp 62/c15 15/b15 4/a8 73/d8
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 8 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. 3v, in-system programming (isp) isp is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic sys- tem before, during, and after its manufacture and shipment to the end customer. isp provides substantial benefits in each of the following areas: design - faster time-to-market - debug partitioning and simplified prototyping - printed circuit board reconfiguration during debug - better device and board level testing manufacturing - multi-functional hardware - reconfigurability for test - eliminates handling of "fine lead-pitch" components for programming - reduced inventory and manufacturing costs - improved quality and reliability field support - easy remote upgrades and repair - support for field configuration, reconfiguration, and customization the xilinx xcr3064a allows for 3.3v, in-system program- ming/reprogramming of its eeprom cells via its jtag interface. an on-chip charge pump eliminates the need for externally-provided supervoltages, so that the xcr3064a may be easily programmed on the circuit board using only the 3v supply required by the device for normal operation. a set of low-level isp basic commands implemented in the xcr3064a enable this feature. the isp commands imple- mented in the xilinx xcr3064a are specified in table 5 please note that an enable command must precede all isp commands unless an enable command has already been given for a preceding isp command. terminations the coolrunner xcr3064a cplds are totalcmos devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. allowing unused inputs and i/o pins to float can cause the voltage to be in the lin- ear region of the cmos input structures, which can increase the power consumption of the device. the xcr3064a cplds have programmable on-chip pull-down resistors on each i/o pin. these pull-downs are automati- cally activated by the fitter software for all unused i/o pins. note that an i/o macrocell used as buried logic that does not have the i/o pin used for input is considered to be unused, and the pull-down resistors will be turned on. we recommend that any unused i/o pins on the xcr3064a device be left unconnected. there are no on-chip pull-down structures associated with the dedicated input pins. xilinx recommends that any unused dedicated inputs be terminated with external 10k ? pull-up resistors. these pins can be directly connected to v cc or gnd, but using the external pull-up resistors main- tains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. when using the jtag/isp functions, it is also recom- mended that 10k ? pull-up resistors be used on each of the pins associated with the four mandatory jtag signals. let- ting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter jtag/isp mode at unspecified times. see the appli- cation notes jtag and isp overview for xilinx xpla1 and xpla2 cplds and terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds for more informa- tion. jtag and isp interfacing a number of industry-established methods exist for jtag/isp interfacing with cplds and other integrated cir- cuits. the xcr3064a supports the following methods: pc parallel port workstation or pc serial port embedded processor automated test equipment third party programmers high-end isp tools table 5: low level isp commands instruction (register used) instruction code description enable (isp shift register) 1001 enables the erase, program, and verify commands. erase (isp shift register) 1010 erases the entire eeprom array. program (isp shift register) 1011 programs the data in the isp shift register into the addressed eeprom row. verify (isp shift register) 1100 transfers the data from the addressed row to the isp shift register. the data can then be shifted out and compared with the jedec file. the outputs during this operation can be defined by the user.
r xcr3064a: 64 macrocell cpld with enhanced clocking 9 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. programming specifications absolute maximum ratings 1 operating range symbol parameter min. max. unit dc parameters v ccp v cc supply program/verify 3.0 3.6 v i ccp i cc limit program/verify - 200 ma v ih input voltage (high) 2.0 - v v il input voltage (low) - 0.8 v v sol output voltage (low) - 0.5 v v soh output voltage (high) 2.4 - v tdo_i ol output current (low) 8 - ma tdo_i oh output current (high) 8 - ma ac parameters f max tck maximum frequency 10 - mhz pwe pulse width erase 100 - ms pwp pulse width program 10 - ms pwv pulse width verify 10 - s init initialization time 100 - s tms_su tms setup time before tck 10 - ns tdi_su tdi setup time before tck 10 - ns tms_h tms hold time after tck 25 - ns tdi_h tdi hold time after tck 25 - ns tdo_co tdo valid after tck -40ns symbol parameter min. max. unit v cc supply voltage 2 ? 0.5 4.6 v v i input voltage ? 1.2 5.75 v v out output voltage -0.5 v cc +0.5 v i in input current ? 30 30 ma t j maximum junction temperature ? 40 150 c t str storage temperature ? 65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must rise monotonically. product grade temperature voltage commercial 0 to +70 c 3.0 to 3.6v industrial ? 40 to +85 c 2.7 to 3.6v
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 10 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v cc 3.6v symbol parameter test conditions min. max. unit v il input voltage low v cc = 3.0v - 0.8 v v ih input voltage high v cc = 3.6v 2.0 - v v i input clamp voltage 3 v cc = 3.0v, i in = -18 ma - ? 1.2 v v ol output voltage low v cc = 3.0v, i ol = 12 ma - 0.5 v v oh output voltage high v cc = 3.0v, i oh = ? 12 ma 2.4 - v i i input leakage current v in = 0 to 5.5 v ? 10 10 a i oz 3-stated output leakage current v in = 0 to 5.5 v ? 10 10 a i ccq 1 standby current v cc = 3.6v, t amb = 0 c-80 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = 0 c at 1 mhz - 1 ma v cc = 3.6v, t amb = 0 c at 50 mhz - 25 ma i os short circuit output current 3 one pin at a time for no longer than 1 second ? 50 ? 200 ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz - 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1 mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1 mhz - 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. this parameter guaranteed by design and characterization, not by test.
r xcr3064a: 64 macrocell cpld with enhanced clocking 11 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v cc 3.6v symbol parameter 710 unit min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 7.5 2 10 ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 39311.5ns t co clock to out (global synchronous clock from pin) 2 5.5 2 7 ns t su_pal setup time (from input or feedback node) through pal 3.5 - 5 - ns t su_pla setup time (from input or feedback node) through pal + pla 5 - 6.5 - ns t h hold time 2 00ns t ch clock high time 2 2 - 2.5 - ns t cl clock low time 2 2 - 2.5 - ns t r input rise time 2 - 100 - 100 ns t f input fall time 2 - 100 - 100 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 250 - 200 - mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 143 - 105 - mhz f max3 maximum external frequency 2 (1/t supal + t co )111-83-mhz t buf output buffer delay time 2 -2-2ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 -5.5- 8ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 2 - 7 - 9.5 ns t cf clock to internal feedback node delay time 2 - 3.5 - 4.5 ns t init delay from valid v cc to valid reset 2 - 20 - 20 s t er input to output disable 2, 3 - 8 - 9.5 ns t ea input to output valid 2 - 8 - 9.5 ns t rp input to register preset 2 - 9 - 9.5 ns t rr input to register reset 2 - 9 - 9.5 ns notes: 1. specifications measured with one output switching. see figure 6 and ta b l e 6 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf.
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 12 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. dc electrical characteristics for industrial grade devices industrial: -40 c t amb +85 c; 2.7v v cc 3.6v symbol parameter test conditions min. max. unit v il input voltage low v cc = 2.7v - 0.8 v v ih input voltage high v cc = 3.6v 2.0 - v v i input clamp voltage 3 v cc = 2.7v, i in = ? 18 ma - ? 1.2 v v ol output voltage low v cc = 2.7v, i ol = 8 ma - 0.5 v v cc = 3.0v, i ol = 12 ma - 0.5 v v oh output voltage high v cc = 2.7v, i oh = -8 ma 2.4 - v v cc = 3.0v, i oh = -12 ma 2.4 - v i i input leakage current v in = 0 to 5.5v ? 10 10 a i oz 3-stated output leakage current v in = 0 to 5.5v ? 10 10 a i ccq 1 standby current v cc = 3.6v, t amb = ? 40 c - 100 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = ? 40 c at 1 mhz - 1 ma v cc = 3.6v, t amb = ? 40 c at 50 mhz - 25 ma i os short circuit output current 3 one pin at a time for no longer than one second ? 50 ? 230 ma c in input pin capacitance 3 t amb = 25 c, f = 1mhz - 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1mhz - 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. this parameter guaranteed by design and characterization, not by test.
r xcr3064a: 64 macrocell cpld with enhanced clocking 13 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. ac electrical characteristics 1 for industrial grade devices industrial: -40 c t amb +85 c; 2.7v v cc 3.6v symbol parameter 10 12 unit min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 10 2 12 ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 3 11.5 3 13.5 ns t co clock to out (global synchronous clock from pin) 2 7 2 8 ns t su_pal setup time (from input or feedback node) through pal 5 - 6 - ns t su_pla setup time (from input or feedback node) through pal + pla 6.5 - 7.5 - ns t h hold time 2 00ns t ch clock high time 2 3 - 3.5 - ns t cl clock low time 2 3 - 3.5 - ns t r input rise time 2 - 100 - 100 ns t f input fall time 2 - 100 - 100 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 166 - 143 - mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 111 - 95 - mhz f max3 maximum external frequency 2 (1/t supal + t co )90-77-mhz t buf output buffer delay time 2 -2-2ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 -8-9ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 2 - 9.5 - 10.5 ns t cf clock to internal feedback node delay time 2 -5-5.5ns t init delay from valid v cc to valid reset 2 -20-20 s t er input to output disable 2, 3 - 10 - 12 ns t ea input to output valid 2 - 10 - 12 ns t rp input to register preset 2 - 10 - 12 ns t rr input to register reset 2 - 10 - 12 ns notes: 1. specifications measured with one output switching. see figure 6 and ta b l e 6 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf.
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 14 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v cc v in v out c1 r1 r2 s1 s2 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t pzh open closed t pzl closed open t p closed closed sp00461b note : for t phz and t plz c = 5 pf, and 3-state levels are measured 0.5v from steady-state active level. figure 6: t pd_pal vs. output switching sp00639 number of outputs switching 1 2 4 8 12 16 v cc = 3.3 v, 25 c 5.3 5.5 5.7 5.9 5.4 5.6 5.8 t pd_pal (ns) 5.2 figure 7: voltage waveform table 6: t pd_pal vs # of outputs switching (v cc = 3.3 v, t = 25 c) # of outputs12481216 typical (ns) 5.3 5.3 5.4 5.6 5.7 5.9 90% 10% 1.5 ns 1.5 ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
r xcr3064a: 64 macrocell cpld with enhanced clocking 15 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. pin function and layout xcr3064a i/o pins (1) jtag pins xcr3064a global, jtag, port enable, power, and no connect pins func- tion block macro- cell pc44 vq44 cp56 vq100 notes 11442c492 12---93 13543c394 14--a196 15--b197 16644a298 17---1 18--a32 1971c14(1) 110-- - 6 111-- - 8 11282d19 11393d310 114115e312 115-- -13 116126f114 2 1 21 15 k5 37 22---36 2 3 20 14 h4 35 2 4 19 13 h3 33 2 5 18 12 k3 32 26--k231 27---30 28--k429 2 9 17 11 k1 25 210-- -23 2 111610j121 212--g320 213-- -19 214148f317 215-- -16 216137g115(1) 3 1 24 18 k7 40 32---41 3 3 25 19 h6 42 3 4 26 20 h7 44 3 5 27 21 h8 45 36--j1046 37---47 3 8 28 22 k9 48 3 9 29 23 k10 52 310-- -54 311--k856 3 12 - - h10 57 313-- -58 3143125g860 315-- -61 3 16 32 26 f10 62 (1) 4 1 41 35 c8 85 42---84 4 3 40 34 a8 83 44--a981 45--a580 46---79 47--a1076 4 8 39 33 b10 75 4 9 38 32 c10 73 (1) 410-- -71 411-- -69 4123731d868 4 133630e867 4 143428f865 415-- -64 4 16 33 27 e10 63 pin type pc44 vq44 cp56 vq100 notes in0 43 37 a6 87 in1 1 39 c6 89 in2 44 38 c7 88 in3 2 40 c5 90 gtsn 44 38 c7 88 (1) clk0 43 37 a6 87 clk1 24 18 k7 40 clk2 21 15 k5 37 clk3 4 42 c4 92 tck 32 26 f10 62 tdi 7 1 c1 4 tdo 38 32 c10 73 tms 13 7 g1 15 vcc 3, 15, 23, 35 9, 17, 29, 41 a4, d10, h1, h5 3, 18, 34, 39, 51, 66, 82, 91 gnd 10, 22, 30, 42 4, 16, 24, 36 a7, e1, g10, k6 11, 26, 38, 43, 59, 74, 86, 95 func- tion block macro- cell pc44 vq44 cp56 vq100 notes
r xcr3064a: 64 macrocell cpld with enhanced clocking ds037 (v1.3) october 9, 2000 www.xilinx.com 16 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. (1) global tri state pin facilitates bed of nails testing without using logic resources. no connects 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78, 99, 100 xcr3064a: 44-pin plcc xcr3064a: 44-pin vqfp pin type pc44 vq44 cp56 vq100 notes plcc 6140 7 17 39 29 18 28 vqfp 44 34 1 11 33 23 12 22 xcr3064a: 56-ball chip scale bga xcr3064a: 100-pin vqfp a1 ball pad corner bottom view a b c d e f g h j k 10987654321 sp00674a vqfp 100 76 1 25 75 51 26 50
r xcr3064a: 64 macrocell cpld with enhanced clocking 17 www.xilinx.com ds037 (v1.3) october 9, 2000 1-800-255-7778 this product has been discontinued. please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. ordering information revision history component availability pins 44 56 100 type plastic vqfp plastic plcc plastic csp plastic pqfp code vq44 pc44 cp56 vq100 xcr3064a -12 i i i i -10 c, i c, i c, i c, i -7cccc date version # revision 9/16/99 1.0 initial xilinx release. 2/7/00 1.1 converted to xilinx format and updated. 9/25/00 1.2 updated pinout tables and features. 10/9/00 1.3 added discontinuation notice. example: xcr3064a -7 pc 44 c temperature range number of pins package type speed options -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay temperature range c = commercial, t a = 0 c to +70 c i = industrial, t a = ? 40 c to +85 c packaging options vq44: 44-pin vqfp pc44: 44-pin plcc cp56: 56-ball chip scale vq100: 100-pin vqfp device type speed options

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